Hiroki Nakahara
(Associate professor at Tokyo Institute of Technology, Japan)

received the B.E., M.E., and Ph.D. degrees in computer science from Kyushu Institute of Technology, Fukuoka, Japan, in 2003, 2005, and 2007, respectively. He has held research/faculty positions at Kyushu Institute of Technology, Iizuka, Japan, Kagoshima University, Kagoshima, Japan, and Ehime University, Ehime, Japan. Now, he is an associate professor at Tokyo Institute of Technology, Japan. He was the Workshop Chairman for the International Workshop on Post-Binary ULSI Systems (ULSIWS) in 2014, 2015, and 2016, respectively. He received the 8th IEEE/ACM MEMOCODE Design Contest 1st Place Award in 2010, the SASIMI Out- standing Paper Award in 2010, IPSJ Yamashita SIG Research Award in 2011, the 11st FIT Funai Best Paper Award in 2012, and the 7th IEEE MCSoC-13 Best Paper Award in 2013, respectively. His research interests include logic synthesis, reconfigurable architecture, digital signal process- ing and embedded systems. He is a member of the IEEE, the ACM, and the IEICE.

Research Interests

Journal Paper

  1. H. Nakahara, T. Sasao, and M. Matsuura, "A packet classifier based on prefetching EVMDD(k) machines," IEICE Transactions on Information and Systems, Vol. E97-D, No. 9, pp.2243-2252. [PDF]
  2. H. Nakahara, T. Sasao, and M. Matsuura, "A heterogeneous multi-valued decision diagram machine for encoded characteristic function for non-zero outputs," Journal of Multiple-Valued Logic and Soft Computing, Vol. 23, No.3-4, pp.365-377. [PDF]
  3. H. Nakahara, T. Sasao, and M. Matsuura, "A virus scanning engine using an MPU and an IGU based on row-shift decomposition," IEICE Transactions on Information and Systems, Vol. E96-D, No.8, pp.1667-1675. [PDF]
  4. H. Nakahara, T. Sasao, and M. Matsuura, "An architecture for IPv6 lookup using parallel index generation units," Lecture Notes in Computer Science,LNCS 7806, pp.59-71. [PDF]
  5. H. Nakahara, T. Sasao, and M. Matsuura, "A Regular Expression Matching Circuit: Decomposed Non-deterministic Realization With Prefix Sharing and Multi-Character Transition," Microprocessors and Microsystems, Vol. 36, No. 8, pp.644-664. [PDF]
  6. H. Nakahara, T. Sasao, and M. Matsuura, "A low-cost and high-performance virus scanning engine using a binary CAM emulator and an MPU," Lecture Notes in Computer Science,LNCS 7199, pp.202-214. [PDF]
  7. H. Nakahara, T. Sasao, and M. Matsuura, "A design method of a regular expression matching circuit based on decomposed automaton," IEICE Transactions on Information and Systems, Vol. E95-D, No.2, pp.364-373. [PDF]
  8. H. Nakahara, T. Sasao, and M. Matsuura, "A comparison of multi-valued and heterogeneous decision diagram machines," Journal of Multiple-Valued Logic and Soft Computing, Vol. 19, No.1-3, pp.203-217. [PDF]
  9. H. Nakahara, T. Sasao, and M. Matsuura, "A regular expression matching circuit based on a decomposed automaton," 7th International Workshop on Applied Reconfigurable Computing (ARC2011), March 23-25, 2011, Belfast. Lecture Notes in Computer Science, LNCS 6578, pp.16-28. [PDF]
  10. H. Nakahara, T. Sasao, M. Matsuura, and Y. Kawamura, "A parallel branching program machine for sequential circuits: Implementation and evaluation," IEICE Transactions on Information and Systems, Vol. E93-D, No.8, Aug. 2010, pp.2048-2058. [PDF]
  11. T. Sasao, H. Nakahara, M. Matsuura, Y. Kawamura, and J.T. Butler, "A quaternary decision diagram machine: Optimization of its code," IEICE Transactions on Information and Systems, Vol. E93-D, No.8, Aug. 2010, pp.2026-2035. [PDF]
  12. H. Nakahara, T. Sasao, M. Matsuura, and Y. Kawamura, "Emulation of sequential circuits by a parallel branching program machine," 5th International Workshop on Applied Reconfigurable Computing,(Lecture Notes in Computer Science, LNCS5443,) Karlsruhe, Germany, March 16-18, 2009.(pp. 261-267, March 2009.) [PDF]
  13. H. Nakahara, T. Sasao, and M. Matsuura, "A PC-based logic simulator using a look-up table cascade emulator," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No.12, Dec. 2006, pp.3471-3481. [PDF]
  14. K. Nakamura, T. Sasao, M. Matsuura, K. Tanaka, K. Yoshizumi, H. Nakahara and Y. Iguchi, "A memory-based programmable logic device using look-up table cascade with synchronous static random access memories," Japanese Journal of Applied Physics, Vol. 45, No. 4B, 2006, pp. 3295-3300. April, 2006. [PDF]
  15. H. Nakahara, T. Sasao, and M. Matsuura, "A design algorithm for sequential circuits using LUT rings," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No.12, Dec. 2005, pp.3342-3350. [PDF]

Conference Paper

  1. H. Nakahara, H. Nakanishi, and K. Iwai, "An AWF digital spectrometer for a radio telescope," 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2014), (Accepted for a publication). [PDF]
  2. H. Nakahara, T. Sasao, and M. Matsuura, "An update method for a CAM emulator using an LUT cascade based on an EVMDD (k)," The 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2014), 2014, pp.1-6. [PDF]
  3. H. Nakahara, K. Iwai, and H. Nakanishi, "A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst," The International Conference on Field-Programmable Technology (FPT 2013), 2013, pp.430-433. [PDF]
  4. A. Matsuo, Y. Takagi, H. Nakahara, S. Yamashita, "A variable-length string matching circuit based On SeqBDDs," The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), 2013. [PDF]
  5. H. Nakahara, T. Sasao, and M. Matsuura, "A packet classifier using parallel EVMDD(k) machine," 7th IEEE International Symposium on Embedded Multicore SoCs (MCSoC-13), 2013, pp.43-48. [PDF]
  6. H. Nakahara, T. Sasao, and M. Matsuura, "A packet classifier using LUT cascades based on EVMDDs(k)," 23rd International Conference on Filed-Programmable Logic and Applications (FPL 2013), 2013, pp.1-6. [PDF]
  7. H. Nakahara, T. Sasao, and M. Matsuura, "A machine to evaluate decomposed multi-terminal multi-valued decision diagrams for characteristic functions," The 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2013), 2013, pp.90-95. [PDF]
  8. K. Shiihara, H. Nakahara, and H. Nakanishi, "Implementation of wide band discrete wavelet transform for a radio telescope," The 22nd International Workshop on Post-Binary ULSI Systems (ULSI2013), 2013, pp.69-71. [PDF]
  9. H. Nakahara, H. Nakanishi, and T. Sasao, "On a wideband fast Fourier transform using piecewise linear approximations: Application to a radio telescope spectrometer," The 12th IEEE International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP2012), Lecture Notes in Computer Science, LNCS 7439, 2012, pp.202-217. [PDF]
  10. H. Nakahara, H. Nakanishi, and T. Sasao, "On a wideband fast Fourier transform for a radio telescope," The 3rd International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2012),(ACM SIGARCH Computer Architecture News) May 31-June 1, 2012, pp.109-114. (Vol.40, No. 5, 2012, pp.46-51) [PDF]
  11. H. Nakahara, T. Sasao, and M. Matsuura, "Multi-terminal multiple-valued decision diagrams for characteristic function representing cluster decomposition," The 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2012), May 14-16, 2012, pp.148-153. [PDF]
  12. H. Nakahara, T. Sasao, and M. Matsuura, "A low power-delay product processor using multi-valued decision diagram machine," The 17th Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI 2012), March 8-9, 2012, pp.394-395. [PDF]
  13. H. Nakahara, T. Sasao, and M. Matsuura, "On a prefetching heterogeneous MDD machine," 54th IEEE International Midwest Symposium on Circuits and Systems(MWSCAS 2011), Korea August 7-10, 2011. [PDF]
  14. H. Nakahara, T. Sasao, and M. Matsuura, "A Comparison of heterogeneous multi-valued decision diagram machines for multiple-output logic functions," International Symposium on Multiple-Valued Logic (ISMVL2011), Tuusula, Finland, May 23-25, 2011, pp.125-130. [PDF]
  15. H. Nakahara, T. Sasao, and M. Matsuura, "A regular expression matching circuit based on a modular non-deterministic finite automaton with multi-character transition," The 16th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2010), Taipei, Oct. 18-19, 2010, pp. 359 - 364. [PDF]
  16. H. Nakahara, T. Sasao, and M. Matsuura, "Packet classifier using a parallel branching program machine," 13th EUROMICRO Conference on Digital System Design (DSD 2010), Lille, France, Sept. 1-3, 2010, pp.745-752. [PDF]
  17. H. Nakahara, T. Sasao, and M. Matsuura, "A regular expression matching using non-deterministic finite automaton," Proc. of Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), Grenoble, France, pp.73-76, July 26-28, 2010. [PDF]
  18. T. Sasao, M. Matsuura and H. Nakahara, "A realization of index generation functions using modules of uniform sizes," 19th International Workshop on Logic and Synthesis (IWLS 2010), June 18-20, 2010, pp.201-208. [PDF]
  19. H. Nakahara, T. Sasao, and M. Matsuura, "A comparison of architectures for various decision diagram machines," 40th International Symposium on Multiple-Valued Logic (ISMVL 2010), Barcelona, Spain, May 26-28, 2010, pp.229-234. [PDF]
  20. H. Nakahara, T. Sasao, M. Matsuura, and Y. Kawamura, "PBM128: A parallel branching program machine consisting of 128 branching program machines," 19th International Workshop on Post-Binary ULSI Systems (ULSI 2010), Barcelona, Spain, May 26-28, 2010. [PDF]
  21. H. Nakahara, T. Sasao, M. Matsuura, and Y. Kawamura, "A virus scanning engine using a parallel finite-input memory machine and MPUs," International Conference on Filed-Programmable Logic and Applications (FPL 2009), Aug.31-Sep.2, 2009. [PDF]
  22. H. Nakahara, T. Sasao, M. Matsuura, and Y. Kawamura, "The parallel sieve method for the virus scanning engine," 12th Euromicro Conference on Digital System Design (DSD 2009), Patras, Greece, pp.809-816, Aug. 27-29, 2009. [PDF]
  23. T. Sasao, H. Nakahara, K. Matsuura, Y. Kawamura, and J.T. Butler, "A quaternary decision diagram machine and the optimization of its code," 39th International Symposium on Multiple-Valued Logic (ISMVL 2009), Okinawa, Japan, May, 2009. [PDF]
  24. T. Sasao and H. Nakahara, "Implementations of reconfigurable logic arrays on FPGAs," International Conference on Field-Programmable Technology 2007 (FPT'07), Dec. 12-14, 2007, Kitakyushu, Japan, pp.217-223. [PDF]
  25. H. Nakahara, T. Sasao, and M. Matsuura, "A hybrid logic simulator using LUT cascade emulators," The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), Sapporo, Japan, Oct 15-16, 2007, pp.135-141. [PDF]
  26. H. Nakahara, T. Sasao and M. Matsuura, "A CAM emulator using look-up table cascades," 14th Reconfigurable Architectures Workshop RAW 2007 (RAW'07), March 2007, Long Beach California, USA. CD-ROM RAW-9-paper-2. [PDF]
  27. H. Nakahara and T. Sasao, "A soft error tolerant LUT cascade emulator," The Fifteenth Asian Test Symposium, (ATS'06), Nov. 20-23, 2006, pp.115-121, Fukuoka, JAPAN. [PDF]
  28. H. Nakahara, T. Sasao and M. Matsuura, "A fast logic simulator using an LUT cascade emulator," 2006 Asia and South Pacific Design Automation Conference (ASPDAC 2006), Yokohama Jan. 2006, pp.466-465. [PDF]
  29. K. Nakamura, T. Sasao, M. Matsuura, K. Tanaka, K. Yoshizumi, H. Nakahara, and Y. Iguchi, "A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs," 2005 International Conference on Solid State Devices and Materials (SSDM 2005), Kobe, Japan, Sep. 2005. [PDF]
  30. H. Nakahara, T. Sasao, and M. Matsuura, "A design algorithm for sequential circuits using LUT rings," The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2004), Oct. 18-19, 2004, Kanazawa, Japan, pp.430-437. [PDF]
  31. T. Sasao, H. Nakahara, M. Matsuura and Y. Iguchi, "Realization of sequential circuits by look-up table ring," The 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, July 25-28, 2004, pp.I:517-I:520. [PDF]

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